The thing inside of us that makes us go up is our attitude.
Design And Reuse - Headline News
The industry source for engineers and technical managers worldwide.

Design And Reuse - Industry Expert Blogs
  • DDR5 Is on Our Doorstep (Breakfast Bytes - Paul McLellan)
    The talk of the town in the DRAM market (well, apart from its growth in the last couple of years) is DDR5. You might assume from the talk that JEDEC has finalized the standard, but it is actually technically still in development. I believe that the final standard is still expected before the end of the year. At TSMC's OIP Ecosystem Forum, Cadence's Marc Greenberg and Micron's Ryan Baxter presented on DDR5 Challenges and Solutions. The two companies decided not to wait for the final ink to dry on the standard since engineering takes too long, so they agreed on a detailed spec that was close to what they expected the final standard to be.
    View the full article HERE

  • Azure for Silicon Design with Cadence and TSMC (Breakfast Bytes - Paul McLellan)
    I used to live on the Cote d'Azur, which is what everyone else calls the French Riviera. The name comes from the blue color of the Mediterranean Sea, azur in French. In English, it is azure. But it is probably more well-known today as the name of Microsoft's Cloud business. Ironically, the dictionary definition of the color azure is "bright blue in color, like a cloudless sky." At last week's TSMC OIP Ecosystem Forum, the invited keynote was by Kushagra Vaid of Microsoft titled Modernizing Silicon Development Using the Cloud. He also gave the invited keynote at CDNLive Silicon Valley in 2017. See my post Microsoft CDNLive Keynote: Cloudy with a Chance of Chips for what he said then. He is GM for Azure Infrastructure for Cloud+AI. Perhaps more importantly for this audience is that he spent a dozen years as a chip designer at Intel. As he said at the CDNLive keynote "I've used plenty of Cadence tools."
    View the full article HERE

  • NXP enhances embedded security and signal processing with new Arm Cortex-M33 based chip families (arm Blogs - Kobus Marneweck, Arm)
    There is no doubt that the next generation of The Internet of Things devices market has exploded, and with that comes the need for the next generation of microcontrollers to support enhanced security, as well as more processing power, while further decreasing power consumption. NXP announced the LPC556x family and the i.MX RT600 crossover processors, both based on the Arm Cortex-M33 processor. This is one of the first Cortex-M processors with Arm TrustZone security technology, bringing a new level of trust to embedded systems. These new NXP microcontroller families represent the next generation of Cortex-M based design, familiar to thousands of developers and used in millions of designs.
    View the full article HERE

  • New CryptoCell Security IP reduces Time-to-Market and meets Chinese Crypto Standards (arm Blogs - Udi Maor, Arm)
    Over the past few years security has become a prominent issue for our partners and their customers. However, OEMs, silicon providers (SiPs) and developers still encounter a number of challenges - as I discussed in my previous blog outlining the Trusted Execution Environment (TEE) challenges in mobile and beyond - when developing security solutions. Some of these challenges include: the increased value of the assets that our devices use daily (e.g. premium content and machine learning (ML) /artificial intelligence (AI) algorithms); the complex regulatory requirements of the Chinese market; and the delay in the time-to-market when security features need integration with existing IP. In addition to these challenges for our partners, according to a soon to be released survey from Arm as part of our updated Security Manifesto, security industry experts think that almost half of consumers are "generally oblivious" to how secure their products are, presenting a consumer education challenge as well.
    View the full article HERE

  • CCIX Over PCIe: Faster Coherent Interconnects for AI, Networking, 4G/5G, and Storage Designs (VIP Experts Blog - Synopsys)
    Next generation SoC designs require faster coherent interconnects for high performance applications such as machine learning, network processing, storage off-load, in-memory data base and 4G/5G wireless technology. CCIX (Cache Coherent Interconnect for Accelerators), a new protocol standard, provides benefits of cache coherency and peer processing which enables the faster interconnect. CCIX is designed smartly to use the well-established PCIe infrastructure to carry coherency packets across the link with little modification. CCIX specification is compatible with PCIe base specification 4.0. PCIe implementation is extended to implement a CCIX transaction layer, responsible for carrying the coherency messages.
    View the full article HERE

  • 7nm TCAM Silicon Testing Exceeds Expectations (eSilicon Blog - Kar Yee Tang & Dennis Dudeck, eSilicon)
    eSilicon’s mission is to enable our partners with high-quality, reliable, silicon-proven IP. Our first 7nm ternary CAM (TCAM) test chip taped out in August 2017 and our silicon testing was completed mid-2018. The TCAM compiler is a vital component in our 7nm FinFET IP Platform for our ASIC customers. The test chip was brought up smoothly (no smoke detectors were triggered) and the silicon results align with the characterization data. A full suite of ATE tests were developed and performed for multiple TCAM configurations and on-chip cycle time, access, setup, hold time, and power measurements correlated. The TCAM is fully functional when operated within 0.8x – 1.3x Vnom. Full memory SCAN and retention test covering down to 0.55V passed.
    View the full article HERE

  • NXP Introduces Tensilica HiFi 4 DSP-based Platforms to Secure IoT Edge Devices (Cadence IP Blog - Paula Jones, Cadence)
    Trust. Privacy. Confidentiality. These are three important concerns for designers of IoT edge devices. Today NXP announced that they are addressing these concerns with two new platforms that feature secure execution environment (SEE) to give developers access to “unprecedented” security capabilities. These platforms provide a multi-layered, hardware-enabled protection scheme to secure IoT edge devices and cloud-to-edge connections. This security, more and more, requires voice activation and recognition. The Cadence Tensilica HiFi 4 DSP “enables efficient local audio pre-processing, immersive 3D audio playback and voice-enables experience.” Our HiFi 4 DSP enhances the NXP platforms’ machine learning (ML) experience with 4x 32-bit MACs, vector FPU, 256-bit wide access bus, and DSP extensions for special activation functions. Yes, machine learning is being designed in everywhere these days. No longer can edge devices just gather data and send it to the cloud. Edge devices need to be smart, and do a lot of the processing on the spot. After all, not all edge applications are Wi-Fi enabled or can rely on consistent communications.
    View the full article HERE

  • The real race for superiority is TSMC vs Intel (SemiWiki - Robert Maire)
    Recent talk of AMD vs Intel market share share is misguided, the real race for superiority is TSMC vs Intel underlying that, tech dominance between US & China. There has been much discussion of late about market share between Intel and AMD and how much market share AMD will gain at Intel's expense due to Intel's very late 10NM technology node. On the surface this may be the minor symptoms of a deeper conflict between Intel and TSMC and ultimately between the US and China for technology dominance. The real root cause of AMD's resurgence also may not be only Intel's stumble but Global Foundries stumble as well. GloFo's stumble in ability to deliver to AMD allowed AMD to go outside of its relationship and hook up with TSMC which "leap frogged" it into a truly competitive position.
    View the full article HERE

  • Meet grandma's new friend: her robot (arm Blogs - Brian Fuller, Arm)
    For the aged, social isolation can be a problem with many unfortunate consequences. Loneliness, for instance, can increase the risk of depression, overall mortality, long-term illness and vastly reduce the quality of life. Combatting the golden years with technology Fortunately, issues faced by aging populations are often top of mind among technology innovators who are developing countless applications and services to combat the physical and emotional challenges of the “golden years.” Introducing ElliQ Take, ElliQ, for example. ElliQ is a robotic companion that learns its owner’s behavior patterns and then suggests activities, music, videos, and ebooks to engage with family and friends to connect with through social media. In short order, robots have evolved from bumping around our floors vacuuming up dust and dirt to serving as human companions.
    View the full article HERE

  • High Resolution Displays for Mobile, TV, PC and Automotive Enabled by DSC 1.2 in HDMI 2.1 (VIP Experts Blog - Synopsys)
    DSC has enabled the use of high resolution displays in televisions, PC monitors, mobiles, and automotive infotainment systems. It provides a high quality, low latency algorithm to resolve the bottleneck of high bandwidth requirements needed to support the high resolution. In our previous blog post, 10K Resolution at 120Hz Display: A Reality Today with DSC 1.2 in HDMI 2.1, we presented how VESA (Video Electronics Standards Association) Display Stream Compression(DSC) embraced HDMI 2.1 to achieve 10K resolutions at 120Hz. In it, we also covered the basic principle of DSC with the help of a diagram which involves dividing the entire frame into slices, replacing a video line with a line of chunks, replacing Hactive (uncompressed pixels) with HCactive (compressed tri-bytes) and replacing Hblank (blanking pixels) with HCblank (blanking tri-bytes). We also mention that HCactive is much smaller than Hactive, which results in compression. In this blog, we will showcase how exactly a frame is divided into slices, how the chunks are formed, and how the DSC model outputs HCactive bytes.
    View the full article HERE

  • Make Versus Buy for Semiconductor IP used in PVT Monitoring (SemiWiki - Daniel Payne)
    As an IC designer I absolutely loved embarking on a new design project, starting with a fresh, blank slate, not having to use any legacy blocks. In the early 1980's we really hadn't given much thought to re-using semiconductor IP because each new project typically came with a new process node, so there was no IP even ready for re-use, at least not at the IDM that I worked at. In 2018 by stark contrast we now have a thriving IP economy providing IC designers with everything starting from simple logic functions at the low-end, all of the way up to processors at the high-end, plus every kind of AMS function that you can imagine. My former Intel co-worker Chris Rowen once famously stated, "The processor is the new NAND gate." So let's say that your next SoC has a power budget, timing specifications and thermal reliability metrics, so you naturally want to have PVT (Process, Voltage, Temperature) monitors placed around your chip in strategic locations so that you can measure and control everything, but should you create your own IP from scratch or just buy something off the shelf? Great question. Let's make a quick list of what it might take to develop your own PVT blocks and start using them:
    View the full article HERE

  • Expanding Innovation: Bringing Arm to Programmable FPGA (arm Blogs - Michele Riga, Arm)
    Today Arm and Xilinx announced a collaboration that makes FPGA-based innovation faster, easier and more diverse: Arm DesignStart FPGA. You can read the announcement here. The design possibilities for embedded and IoT are wider and more accessible than ever with free, no-royalty use of Arm Cortex-M soft processor IP on Xilinx FPGAs. Now developers can access the benefits and ecosystem of Arm Cortex-M processors with the flexibility of FPGA. Let's take a look at what's included and how to get started.
    View the full article HERE

  • Arm Delivers a Comprehensive Physical IP Platform for Optimized SoCs with TSMC 22nm ULP/ULL Process Technology (arm Blogs - Geetha Rangarajan, Arm)
    During the 2018 TSMC Technology Symposium USA event, Arm’s Physical Design Group introduced its development plans for the Artisan physical IP portfolio on TSMC’s 22nm ultra-low power (ULP) and ultra-low leakage (ULL) process platforms. With an aggressive development schedule and a broad range of IPs, our enthusiasm for accelerating SoC designs has resulted in early access for our mutual customers to explore what the Artisan products and the TSMC 22nm process technologies can achieve for their complex SoC designs. The initial announcement of the Artisan physical IP for TSMC 22nm ULL and ULP platforms included a key component - a dozen foundry sponsored memory compilers spanning the two TSMC 22nm process nodes. In addition, Arm’s own Artisan standard cell and general purpose I/O (GPIO) libraries are available for these 22nm platforms. Our teams have worked intensively to expedite the library deliverables, which means our customers can start their design evaluations now. Several of our lead silicon partners have already benefited from this close collaboration between Arm and TSMC, and are on their way towards taping out their first ultra-low power SoCs. We will share more exciting updates at Arm TechCon on October 16-18. Come join us!
    View the full article HERE

  • AutoSens 2018 show report: another 5 lessons learned (videantis Blog - Marco Jacobs)
    It seems like it was only yesterday that Robert Stead from Sense Media organized his first AutoSens conference, but time flies when you’re having fun, and last week it was already the fifth AutoSens show that took place. Special pins were handed out to the select group of people that had attended all five shows.
    View the full article HERE

  • Behind the Scenes: The Universe's First DisplayPort 1.4Tx IP Solution (Probably) (Certified to0!) (To USB or Not to USB: A USB IP Blog - Eric Huang, Synopsys)
    Hey USB and DisplayPort fans! I’m excited to announce Synopsys’ DisplayPort 1.4Tx IP solution (probably), which we demonstrated three months ago. And (probably) the first certified DP 1.4 Tx IP solution. |youtubevideo:3wUPkqZ6jBc| Why is Certification and Interoperability Important for IP? Certification and interoperability prove that an IP can pass testing with the right implementation. If the IP passes the test, this proves a proper implementation will pass testing. IP that passes certifcation has a higher probability of interoperating with other products that pass the same protocol, electrical and interoperability tests.
    View the full article HERE

  • 56G 7nm SerDes: Eye-Witness Account (eSilicon Blog - Mike Gianfagna, eSilicon)
    High-performance SerDes represents critical enabling technology for advanced ASICs. This star IP block finds application in many networking and switching designs as well as other high-performance applications. So, when a new high-performance SerDes block hits the streets, it’s real news. eSilicon has been enjoying the spotlight on such an event. We recently announced silicon validation of our 7nm, 56G long-reach SerDes. We were happy to report in that announcement: “lab measurements confirm that the design is meeting or exceeding the target performance, power and functionality.” Anyone who has plugged a new and complex chip into a test fixture for the first time knows what this feels like.
    View the full article HERE

  • GTC: GlobalFoundries Pivots (Breakfast Bytes - Paul McLellan)
    Tuesday was the GlobalFoundries Technology Conference GTC. GF announced earlier in the month that they are dropping 7nm and are focusing all their effort on differentiated processes, in particular FDX (see my post GLOBALFOUNDRIES Drops 7nm to Focus on Other Geometries). In March, Thomas Caulfield was appointed GF's CEO. Ironically, as the manager of fab 8, he was in charge of ramping GF's 7nm efforts that were scheduled to be in volume production in 2019. So dropping 7nm was, in a sense, killing his own baby. GF calls it "the pivot" (or "the pivot to relevance") and it even has its own logo. At GTC, Tom explained the pivot.
    View the full article HERE

  • The Real Case of Silicon-as-a-Service - A Tale of 3 Innovators (Algodone Blog - Jin Zhang, VP of Marketing, Algodone)
    We, at Algodone, have been talking for a while now about the oncoming of the new business model for the semiconductor industry, “Silicon-as-a-Service”. It is based on the insight and belief that for the last couple of decades, the world is moving rapidly towards an as-a-service economy. To stay nimble and relevant in the fast-changing world, the semiconductor companies also need to reinvent themselves and adapt. Following this vision, Algodone’s founders, Jerome, Gael and Lionel, built the company and developed the Silicon Activation Licensing Technology (SALT TM) that is to become the enabler for this transition. It has been 3 years in the making, and the day we have all been waiting for has finally come. September 10th, 2018 marks a ground-breaking moment that our vision has come true. SALT, which symbolizes a necessary ingredient for our everyday life, has been deployed in real customer production. In this exciting tale, it takes three to tango - three remarkable innovators working together to pave the way for all others to follow –  The trail blazer who is willing to walk the unknown and open a new chapter for the business of the semiconductor companies. Our hero here is NGCodec®, a leader in cloud video processing, who sees the same trend and seizes the opportunity to charter into the Silicon-as-a-Service, pay-per-use business model. Instead of selling its advanced video encoding technology as a product, NGCodec licenses its technology accelerated on FPGAs and bills customers based on volume of data processed through their video encoder. For that, it needs a platform that allows them to easily deploy and manage their video encoding products in the cloud (Public, Private, On-premise, or any mixture of the flavor). That brings us to the company Accelize®.  Accelize is the leading provider and enabler of FPGA Accelerator functions in the cloud. Their Digital Right Management (DRM) Platform allows NGCodec to securely address the need for as-a-service purchasing model from their customers, while focusing on developing its core competency on video encoding without having to worry about managing the logistics in complex, hybrid multi-cloud environments. At the heart of this DRM platform is a silicon-based licensing scheme created by Algodone, the 3rd innovator in the success story.  Algodone’s Silicon Activation Licensing Technology (SALT) includes a DRM controller that is used by Accelize for integration inside the NGCodec’s video encoding design; and a license provisioning software, also part of the Accelize platform. The combination of the silicon and the license guards against illegitimate uses of NGCodec’s technology and at the same time enables legitimate use of processed video while metering usage for billing. Without this core innovation, there would be no Silicon-as-a-Service, because protection and metering are two key elements that make it a viable and profitable solution. Oliver Gunasekara, CEO of NGCodec, said in the press release: “Today, our customers want instantaneous access to our technology and the ability to pay only for what they use.” Indeed, today consumers’ on-demand, pay-per-use, anytime and anywhere mindset is driving and reshaping the broad market place. With NGCodec blazing the trail and showing the industry that Silicon-as-a-Service can be done, both in terms of business model, and in term of the necessary enabling technologies, it won’t be long before other companies in AI, Automotive, Healthcare, Education, and IoT spaces, where security and user experiences matter, follow suit. September 10th is the teachers’ holiday in China. It is fitting that this day, with this announcement, also signifies a teaching moment for the industry, that you too can be brave and adopt Silicon-as-a-service. We, Algodone and Accelize, working together, are ready for you to take your business to the next level.
    View the full article HERE

  • Arm Competing With Its Customers (Mannerisms - David Manners)
    As Arm moves to compete with its customers, is it pushing its customers towards RISC-V? One of the oldest rules of the semiconductor industry is: Don’t compete against your customers. This is all the more important if you’re an IP company where your toe-hold in a customer’s product plans can often be replaced pretty easily. One of Arm’s great strengths was that its first two CEOs were trusted by its customers not to give preferential treatment to any other customer and not to compete with its customers.
    View the full article HERE

  • The importance of "Trust, but verify" (UltraSoC Blog - Aileen Smith, UltraSoC)
    SoC security is all about layers of trust. UltraSoC CSO Aileen Smith takes some lessons from real life, and argues for the use of hardware-based security to create more sophisticated trust models. The phrase ‘Trust, but verify’ came to prominence during the Reagan administration, but is entirely relevant today in the era of “fake news”. As the parent of a toddler I entrust the care of my child to another adult while I am at work. However, before doing that, I need to verify some information about this person. Are they really who they say they are? There are some rudimentary “fact checking” ways to verify and build a first level of trust – DBS checks with the police, reference checks with previous employers, qualification checks for items like first aid certification etc.
    View the full article HERE