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  • UPF Versioning Nightmare Solved (Sonics, The Official Blog - Greg Ehmann, Sonics)
    Unified Power Format (UPF) has been an ever evolving standard started as a technical committee by the Accellera organization in 2006, producing the first revision of the UPF specification, UPF 1.0 in 2007. Soon after UPF 1.0 release the group reformed under the IEEE organization as IEEE1801 with a major goal of merging in a competing standard, the Common Power Format (CPF). IEEE 1801 has since released three new versions of the UPF specification over the past ten years: IEEE1801-2009 (UPF 2.0), IEEE1801-2013 (UPF 2.1) and IEEE1801-2015 (UPF 3.0). UPF solves some unique problems in the design world. One is the lack of any need to consider power supplies in traditional digital design at the RTL level (or higher). Others cope with the desire to separate what is supported by an IP component from what is actually implemented on a given chip. From an IP developer’s view: How can I provide one functional description and let my user choose what power features to use and how to implement them? From a chip architect’s view: How can I describe the power structure on a chip without having to embed the architecture into every block of the functional description?
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  • When Invaluable Kills Business (SemiWiki - Frederic Leens)
    Productivity is notoriously hard to sell. I recently visited a company where the engineering team wanted to evaluate one of our FPGA debug and analysis products on an existing board. This board had an FPGA that we supported and had all the required connectivity - it could just be used ‘out of the box’. Our tool - Exostiv - involves the insertion of a debug IP in the FPGA. We offered to set up the tool with the engineering team and within 60 minutes, the board was instrumented and ready to use. As I did it by myself, there was no initial setup cost nor learning curve cost in this example. Well, a good demonstration as it seemed... After 2 hours of discussion and having shown the product's main features, I left the engineering team a unit with a license until the next day. The next day, the engineering team told me that the tool was easy to use for those used to JTAG-based logic analyzers such as Chipscope / Xilinx logic analyzer. Basically, the flow was identical. Specific items like transceivers configuration required some additional understanding of the parameters, but overall, they said the setup and trial had run pretty smoothly.
    View the full article HERE

  • Arm AMBA 5 AHB5: Accelerating the Embedded and IoT World (VIP Experts Blog - Synopsys)
    Ever since Arm® released the AMBA® 5 AHB5 protocol specifications, questions have arisen among users in the design and verification community—”Why AHB5?”, “What is new in AHB5?” etc. This post initiates a short series of blogs in which we will address these questions and introduce the new features of AMBA 5 AHB5. Why AMBA 5 AHB5?
    View the full article HERE

  • USB 3.2 Cable Lengths and Water Delivery (To USB or Not to USB: A USB IP Blog - Eric Huang, Synopsys)
    From USB 2.0 to USB 3.2, USB cables became shorter. When USB replaced keyboards and mice, USB’s signaling rates of 1.5 Mbps and 12 Mbps. Transmitted more than enough data. If you know what a floppy disk is, those stored data in the Megabytes. When USB 2.0 launched in 1999 it maintained the 5 meter cable length. With USB 3.0 the cable length dropped to about 2-3 meters for 5 Gbps. And with USB 3.1 it dropped to 1 meter for 10 Gbps. USB 3.2 cables can be 1 meter because it uses 2 lanes of 10 Gbps. The PHY / electrical signaling for USB 3.1/3.2 is exactly the same so cables can stay the same length.
    View the full article HERE

  • RISC-V Business (SemiWiki - Daniel Nenni)
    I was at the 7th RISC-V Workshop for two days this week. It was hosted by Western Digital at their headquarters in Milpitas. If you have not been following RISC-V, it is an open source Instruction Set Architecture (ISA) for processor design. The initiative started at Berkeley, and has been catching on like wildfire. There are a number of RTL implementations that work in FPGA’s or SOC’s and there is also production silicon from companies such as Si-Five. The RISC-V Workshop was sold out with over 500 attendees – most of whom stayed for the full two days.
    View the full article HERE

  • What are you ready to mobilize for FPGA debug? (SemiWiki - Daniel Nenni)

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  • Silexica: Mastering Multicore (Breakfast Bytes - Paul McLellan)
    Since the invention of the microprocessor, it was a dream that it would be possible to build a really powerful computer by taking a lot of cheap simple computers and putting them together. This was especially a dream of hardware designers, who could see their way to addressing the hardware problems, and then the rest was "just" software. That software turned out to be difficult to create. About a decade ago, it became clear that microprocessor clock frequencies could no longer be increased and companies like Intel switched to multi-core processors. However, that software was still not easy to write, and it was hard to make use of large numbers of cores for individual jobs. There were some tasks that work well on this sort of fabric. Some programs are "embarrassingly parallel" with almost limitless opportunities. The standard example is graphics where each pixel can sometimes be processed individually, with reference only to a few nearby pixels. In fact, it is this that allows GPUs to function, since even when dealing with polygons and shading, it is still the case that one part of the image is largely independent of parts that are not in the immediate neighborhood.
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  • Check Again: Cadence Announces Release of the First PCIe 5.0 VIP - With TripleCheck! (Functional Verification Blog - Team Specman, Cadence)
    On November 28, 2017, Cadence announced the release of the first available PCIe® 5.0 Verification IP. This new VIP gives designers access to Cadence’s TripleCheck technology—which gives designers a comprehensive verification plan that uses measurable objectives related to spec features, along with a test suite containing thousands of tests. These combine to greatly improve the speed and quality of functional verification runs for server and SoC designs using the PCIe 5.0 specification. It also gives designers access to the Indago Protocol Debug App.
    View the full article HERE

  • Imagination's Question of the Month: Is AI overhyped? (With Imagination Blog - Benny Har-Even, Imagination Technologies)
    Welcome to the first of new series of blog posts where on a monthly basis we will be exploring some of the big issues facing the industry right now. We will do so by asking a question to experts in the industry and also the expertise within our company. The first question is simply: “is AI overhyped?” Imagination recently entered the world of AI-related industry with the recent announcement of its neural network accelerator (NNA), the PowerVR Series2NX. This offers hardware acceleration of neural networks at unprecedented levels of performance and will enable upcoming embedded and mobile devices to take advantage of neural network powered AI applications. But has too much stock been placed in AI as a whole? As you will no doubt be aware, AI is taking over headlines everywhere with the promise to reorganise, revitalise and revolutionise our world. Of course, there are arguments for and against and many prominent, public figures have expressed their concerns over its potential impact. Just this week Hilary Clinton stated that America was, ‘totally unprepared’ for the impact of AI, while the likes of Elon Musk and Stephen Hawking have both expressed their deep fears over where it could leave the human race. So what does Imagination think? Rather than presenting a single unified answer in this post we get the personal views of five members of our staff.
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  • Now is the Time for eFPGA Technology (GLOBALFOUNDRIES Foundry Files Blog - Timothy Saxe, QuickLogic)
    Embedding FPGA technology into SoC designs isn’t really a new idea. In fact, at QuickLogic we’ve been doing it for nearly two decades, starting with our FPGA/hard PCI controller SoC all the way back in 1999. The value proposition was the same then as it is now. Higher levels of integration delivering a higher level of functionality, performance, and design flexibility with lower cost, power consumption, and board space requirements. So why hasn’t eFPGA technology taken off much sooner? The answer lies fundamentally in the relationship between die costs and development costs. Let’s start with die sizes and costs. Our PCI device in 1999 employed a 0.35 micron process which used 24,650 square microns per logic cell. By 2002, the 180nm process we used for our QuickMIPs device resulted in 9,306 square microns per logic cell – less than half the area for more FPGA capability. Today our latest device, the EOS™ S3 Sensor Processing Platform, includes an even greater level of FPGA capability with a die area of just 961 square microns per logic cell through the use of a 40nm process technology. That’s roughly a factor of 25 reduction in the die area of the eFPGA portion of these devices over the last 18 years.
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  • Worldwide Interface IP Revenue Grew by 13.5% in 2016 (SemiWiki - Eric Esteve, IPnest)
    IPnest has released the 9th version of the Interface IP Survey, ranking by protocol the IP vendors addressing the Interface segments: USB, PCI Express, (LP)DDRn, MIPI, Ethernet & SerDes, HDMI/DP and SATA. When the 1st version has been issued in 2009, the IP segment was weighting $225 million and the 2009 to 2008 growth was negative due to the 2008 economic crisis. The same segment has generated $550 million in 2016! As you can see on the below chart, Synopsys is clearly leading with 49% market share, followed by Cadence and Avago, each company enjoying about 10% market share, Rambus and Faraday ending this top 5 with less than 5% market share. In fact, as the interface IP market is essentially made of up-front license, IPnest has not included royalty in this ranking. If we take royalty into account, Rambus share would grow up to the Cadence level.
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  • Bit Error Rates for USB 3.2 (To USB or Not to USB: A USB IP Blog - Eric Huang, Synopsys)
    Bit Error Rates and Snoopy’s rejection letters Bit Error Rates (BER) in wired and wireless communication communicate the “allowable” or target number of errors (rejected or non-transmitted data) that can occur over some given time. Usually this is measured of a period time like a second. Wired interfaces enable faster speeds because a hard wire has less ways it can be interfered with on the path from one product to another. Even wired interfaces like USB and Ethernet, basically any wired interface port, generates https://en.wikipedia.org/wiki/Electromagnetic_interference which can interfere with data transmission inside or outside the device. For example, Electromagnetic Interference (EMI) in PCs is tightly regulated by the FCC in the U.S. For USB specifically, the BER tolerance is low because it’s a wired interface. The FCC does not regulate hair dryers and thus can emit enough EMI to bring down a nuclear power plant.
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  • CCIX Update: TSMC, Xilinx, Cadence, Arm...and Jasper (Breakfast Bytes - Paul McLellan)
    CCIX (pronounced see-six) is the Cache Coherent Interconnect for Accelerators. I wrote about it in my post CCIX is Pronounced C6 and also when Cadence announced its collaboration with TSMC, Arm and Xilinx in Xilinx/Arm/Cadence/TSMC Announce World's First 7nm CCIX Silicon Demonstrator. There have recently been a couple of updates. First, at Arm TechCon on the foundry afternoon, TSMC, Cadence, Xilinx and Arm all gave some background on their collaboration. Then, at the Jasper User Group (JUG) held recently, Cadence's IP group talked about using formal approaches to verify their implementation of CCIX IP that is inside the demonstrator chip.
    View the full article HERE

  • Is Your Design PCIe Gen5 Ready? Verify with Synopsys VIP and Testsuite (VIP Experts Blog - Synopsys)
    In June 2017, PCI-SIG announced the new PCI Express 5.0 specification, at the PCI-SIG DevCon. The new version of the specification doubled bit rate to 32GT/s per lane providing about 128GB/s bandwidth for a x16 Link (16 lanes). The chart below provides a comparison of bit-rate and bandwidth for the different PCIe Generations.
    View the full article HERE

  • MIPI Solutions for Automotive, IoT and Mixed Reality (VIP Experts Blog - Synopsys)
    This year, MIPI DevCon was held in Bangalore, India and Hsinchu City, Taiwan in October. Synopsys MIPI protocol experts hosted several demos at each conference showcasing implementation experiences, use cases and application examples within mobile, automotive, IoT and mixed reality applications.
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  • Foundry Roadmaps: Intel, Samsung (Breakfast Bytes - Paul McLellan)
    I definitely had cognitive dissonance at the ARM foundry talks at TechCon. The first thing was that the organizer of the sessions was Kelvin Low. Since he was the marketing guy for Samsung Foundry until summer before joining Arm as their VP of marketing for physical libraries, it was odd to see him introduce Tom Quan of TSMC. Perhaps even more unusual was when Kelvin introduced Robert Stear of Intel Custom Foundry. I don't recall seeing Intel at TechCon ever before.
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  • A cool video on USB 3.2 and USB 3.2 Primer Part 2 (To USB or Not to USB: A USB IP Blog - Eric Huang, Synopsys)
    Today, on Thursday, (what I call 2nd Wednesday), I’ll write about Isochronous over USB 3.2. Before that, Our Super PHY Guy, Gervais Fong, (Product Marketing Manager for USB and DP PHYs) has an great introduction to USB 3.2. Watch the video first.
    View the full article HERE

  • Higher Mobile Storage Performance at Lower System Cost (VIP Experts Blog - Synopsys)
    Higher storage performance at a lower cost can create a bottleneck in the design of storage devices. In order to achieve higher performance, devices must use on chip DRAM, which adds to the overall cost. This is where Unified Memory Extension (UME), a JEDEC specification, comes into the picture. It is defined as extension to the JEDEC UFS (Universal Flash Storage) specification. JEDEC UFS device uses NAND flash technology for data storage. Unified Memory (UM) allows users to use part of the host memory as the device’s internal memory. Since the host memory is already available in large capacities, this mechanism provides a much bigger space for the device to use as a Write Buffer (WB) cache or to store information such as Logical to Physical (L2P) address translation tables. The UM area is physically located on the host side but ultimately belongs to the device, thereby replacing the device-integrated RAM, and reducing overall cost. Large space availability means the device can store larger amounts of WB of L2P table information resulting in higher storage performance.
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  • Synopsys Enhances ARC Processor Core With Superscalar, DSP Capabilities (Inside DSP - BDTi)
    By adding a second front-end instruction decoder to the ARC HS3x high-end 32-bit RISC architecture, along with doubling the number of ALUs, Synopsys has created its latest ARC HS4x processor IP core family (Figure 1). The estimated performance increase over an ARC HS3x predecessor at the same clock speed can be as high as 40%, according to the company, with only modest die size and power consumption impacts. And via the inclusion of DSP enhancements akin to those initially launched with the mid-range ARC EMxD family, the HS3x-to-HS4xD (D=DSP) performance boost on code leveraging the associated expanded instruction set can be as much as 2x.
    View the full article HERE

  • New Arm CoreSight SDC-600 for secure, authenticated debug (arm Blogs - Lip-Min Khor, Arm)
    The history When it comes to security, the main objective is to establish trust. Trusting users can be subjective and ambiguous, therefore modern technology has been designed to give different types of users different level of trust, and formulate corresponding mitigation measures. The designers of every new application and device need to consider the cost-benefit ratio of adding security features. All security can eventually be breached given sufficient time and resource, therefore a primary goal is to increase protection and security to a level where an attack on a device is deemed uneconomical. Arm IP can be found in billions of electronic devices today, ranging from low-end IoT sensors to high-end enterprise hardware. The real value doesn’t lie in the physical device, but in the data contained inside. An example of this could be in the medical industry. In recent times, vulnerabilities have been discovered in embedded medical electronic devices, exposing an urgent need to improve security to protect patients and hospital infrastructure. The potential attack surface grows every day, thanks to the ever-expanding network of connected devices. Thus, security needs to be considered and implemented for all elements - from a secure handshake with trusted agents, right down to data encryption to prevent unauthorized accesses to sensitive information. One of the most common parts of the system frequently compromised for attacks is the debug element.
    View the full article HERE