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Design And Reuse - Industry Expert Blogs
  • The Continuing Evolution of Moore's Law (EETimes Blog - Michael Mayberry, CTO, Intel Corp.)
    CMOS scaling is not yet done, and we can see continued progress as we improve our ability to control fabrication. Moore’s Law is dead – Long live Moore’s Law! This was the essence of the debate at DARPA’s Electronics Resurgence Initiative (ERI) Summit in San Francisco. But to understand the debate, we need to agree on what is meant by Moore’s Law. Gordon Moore’s original observation in 1965 was that as you packed more functions into an integrated circuit, the cost per function decreased. The first part of this observation is about economics, and its essence has remained constant even as the underlying technology and rate of improvement has evolved.
    View the full article HERE

  • Our 56Gbps PAM4 SerDes IP Hits the Lab (eSilicon Blog - Tim Horel, eSilicon)
    At eSilicon we’ve been talking about adding a 56G PAM4 SerDes to our N7 ASIC IP platform now for some time. I’m happy to say our 7nm FinFET 30 Gbaud/s PMA test chip silicon is now in the lab and we have lots of good news to share! We’ve successfully passed the smoke test (none escaped – all good!) and are romping through the full set of registers. All of the sub blocks have now been brought up operationally and are fully functional with their performance data showing all parameters are inside the pre-silicon modeling and calibration bounds. Detailed characterization of each is now under way. On the speed front, both the Tx and Rx circuitries have been shown to operate over the full frequency range targeted by the design. Power consumption of the silicon as compared to models is always a concern. Here we have been able to show it is as low as had been predicted.
    View the full article HERE

  • Arm succumbs to Californification (Mannerisms - David Manners)
    Poor old Arm. Once respected across the world for designing processor cores which the world wanted to use and developing the physical IP to implement them, the company is succumbing to Californification. What would a bunch of engineers designing processor cores want with a Californian ‘analytics’ company?
    View the full article HERE

  • Architecting a more Secure world with isolation and virtualization (arm Blogs - Berenice Mann, Arm)
    New Secure world architecture in Armv8.4 Arm TrustZone was introduced to the Arm architecture A-profile in 2003. At the heart of the TrustZone approach is the concept of Secure and Normal worlds that are hardware separated. Secure hardware resources are only accessible by the software running in the Secure world. Software in the Normal world is blocked by the hardware from accessing these resources. This concept of Secure (trusted) and Normal (non-trusted) worlds extends beyond the processor, to encompass memory, software, bus transactions, interrupts and peripherals within a System on a Chip (SoC). The introduction of TrustZone has paved the way for an ecosystem of trusted operating systems (OS) vendors. Initially, trusted OSs provided basic device security services, such as trusted boot, or handling of platform secrets. Today, trusted OSs have evolved to support bespoke applications that might be used in a variety of security use cases, such as secure payment or media protection.
    View the full article HERE

  • NetSpeed and Arm Partner to Create ASIL D Safety Islands for Autonomous Vehicle Applications (arm Blogs - Andrew Hopkins, Arm)
    Autonomous driving is a catalyst for revolutionary change in the automotive industry, where semiconductors are a decisive enabler. Elevated requirements for functional safety, large scale data and complex decisions are already motivating changes in System-on-Chip (SoC) design and processor architecture. Arm and NetSpeed recognize this technology shift and are working together to enable better systems.
    View the full article HERE

  • PCIe 5.0 Demos: IP and VIP for AI, Cloud, Storage, and Networking (VIP Experts Blog - Synopsys)
    This year’s PCI-SIG Developers Conference took place at the Santa Clara Convention Center on June 5-6. Synopsys provided several demos covering the PCIe 5.0 Integrated IP Core, PHY, and Verification IP & source code Test Suites. There was a constant pool of inquisitive attendees interacting with our PCIe design and verification experts regarding the demos. The Verification demo was centered around the PCIe 5.0 VIP acting as a Root Complex talking to our Integrated IP for PCIe 5.0 Endpoint. We specifically highlighted one of our PCIe 5.0 tests from the UVM source code test suites. The demo walked users through linkup and training including equalization. The test executed configuration of the BAR and then a series of DMA transfers. The demo also showcased natively integrated Verdi Protocol Analyzer for easy and fast transaction level debug.
    View the full article HERE

  • Turning Fixed Costs into Variable Costs: Foundries and Clouds (Breakfast Bytes - Paul McLellan)
    One trend that has been accelerating for a couple of decades is turning fixed costs into variable costs. Often this is what is behind outsourcing some capability. Sometimes it is driven purely by lower variable costs (let's hire a team in Shanghai) or core-competence considerations (we don't really need to run our own cafeteria). However, often it is driven by a desire to switch an inflexible fixed cost for a variable cost. The biggest of these trends in our industry is the foundry/fabless model. Instead of a semiconductor company building their own fab (fixed cost), they buy wafers from foundries (variable costs).
    View the full article HERE

  • I've Looked at Clouds from Both Sides Now (Cadence on the Beat Blogs - Meera Collier, Cadence )
    —Joni Mitchell Unless you really haven’t been paying attention, everyone is talking about the cloud, and the EDA world is no exception. At DAC last month, the two main themes were machine learning and EDA in the cloud. (Paul’s recent blog posts about DAC, including DAC Monday, Tuesday, and Wednesday, and the "Straight Talk" discussion with Lip-Bu Tan will give you more of an idea.) I’ve written extensively about ML/DL, but haven’t touched much on the cloud yet. So let’s talk about it.
    View the full article HERE

  • Trends, Technologies, and Regulations in China's Auto Market (Breakfast Bytes - Paul McLellan)
    At "Ludwigsburg", officially the International Autombil Elektronik Kongress, there was a push this year to be more international. In particular, attendees last year had asked for a deeper perspective on what is happening in the largest automotive market of all. There were several presenters who covered different aspects of the market and I learned a lot from very basic facts (all interenal combustion cars in China have to be kept off the road one day per week) to more technical (self-driving cars in China assume that there will be a 5G network that can be relied on). The most comprehensive presentation was by Dr Volkmar Tenneberger who works for the VW Group in China, and I stole his title for the title for this blog post. It is easy to fall into the trap that the market you know best is the leader in some sense, and China, still being relatively poor, is not yet that significant. But here are a few statistics Volkmar presented to show just how big markets are in China. The per-capita GDP may be lower than the US or Western Europe, but there are a lot of capita. All data in this table is 2017, so it is pretty much up to date.
    View the full article HERE

  • A Starter's Guide to Arm Processing Power in Automotive (arm Blogs - James Scobie, Arm)
    Co-authored by James Scobie and Govind Wathan The automotive industry is rapidly transforming, with technology driving innovation, automotive standards shaping requirements and consumer preferences changing demands. These factors are significantly impacting all automotive applications from Advanced Driver-Assistance Systems (ADAS), autonomous drive, In-Vehicle Infotainment (IVI) and digital cockpit, to powertrain and chassis. Arm offers a broad range of different classes of processor, specifically designed to address the needs for each of these automotive applications. To help you take advantage of this processing power, here is a guide to how Arm’s different classes of processors can be applied to various automotive applications.
    View the full article HERE

  • Clouds Roll Through Electronic Design Ecosystem (EETimes Blog - Bob Smith, ESD Alliance )
    Design tool vendors, especially in the verification space, are starting to roll out cloud-based solutions. Cloud computing offers faster results, unlimited capacity during peak demand, elasticity to scale with that demand, and reduced capital expenditures. As recently as five years ago, engineers did their personal banking and purchased almost everything online but wouldn’t consider loading their chip designs into the cloud. Clouds are forming over the electronic product design ecosystem and finally rolling through, offering viable choices for on-demand, high-performance computing without the investment of capital and human resources traditionally needed to manage a captive server farm. The change in mindset of chip design and verification engineers is nothing short of remarkable and well worth exploring why.
    View the full article HERE

  • India and RISC-V: tasty ecosystems, fast data, and bright futures (UltraSoC Blog - Aileen Smith, UltraSoC)
    Last week I attended the inaugural Indian RISC-V Workshop in Chennai, hosted by the Indian Institute of Technology Madras (IIT). For myself and my colleague, UltraSoC CTO Gajinder Panesar, our goals were to understand more about the state of the Indian semiconductor market and to connect with partners and prospects, as well as enjoying the culture and eating some great Indian food. We managed to tick all those boxes, and more! There was an energy and excitement in the air at the event, a sense of a community on the cusp of something big, something important, a spirit of collaboration as we build something new together. The Indian government has strongly endorsed the RISC-V standard, which is being embraced not only in the Indian academic world but also the governmental technology units (defense, space etc.) and the rapidly growing local semiconductor industry which boasts a healthy design service sector and a vibrant start-up community with particular emphasis on the IoT space.
    View the full article HERE

  • FDSOI Status and Roadmap (SemiWiki - Scotten Jones)
    FDSOI is gaining traction in the market place. At their foundry forum in May, Samsung announced they have 17 FDSOI products in high volume manufacturing. At SEMICON West in July, GLOBALFOUNDRIES (GF) announced FDSOI design wins worth $2 billion dollars in revenue with $1 billion dollars booked in 2017 and another $1 billion dollars in revenue booked in the first half of 2018. With the emergence of FDSOI I thought it would be useful to review who the players are in the market and what their current and planned processes look like.
    View the full article HERE

  • Evaluating EDA Functional Safety in the AV Era (EETimes Blog - Joseph Dailey (Mentor, a Siemens business))
    In the EDA industry, a fierce battle is underway around functional safety. Surprisingly, though, the "big three" EDA houses maintain quite distinct approaches to helping chipmakers prove ISO 26262 compliance. As cars continue their transformation from glorified, mechanical horseless carriages to AI-powered robots on wheels, the global auto industry is increasingly looking to the semiconductor market to provide the embedded intelligence necessary to realize the era of assisted and autonomous driving. Meanwhile, the auto industry’s long-running obsession with reliability and functional safety continues unabated. The “north star” for establishing the reliability of E/E automotive systems is ISO 26262, the international standard for functional safety of electrical and/or electronic systems in production automobiles. Automakers and their Tier 1 suppliers are pushing semiconductor providers to deliver ISO-26262-compliant ICs together with evidence that the tools used to create the chips have qualified for the standards as well.
    View the full article HERE

  • Companion chips: The intelligent choice for AI? (With Imagination Blog - Simon Forrest, Imagination)
    For many years, the semiconductor industry has strived towards tightly integrating more and more components into a single system-on-chip (SoC). After all, it is an entirely practical solution for high volume applications. By optimally positioning the various cores, memories and peripherals chip manufacturers are able to minimise data pathways, improve power efficiency and optimise for high performance, while significantly reducing costs. The industry has very much succeeded with this approach and the SoC is now a standard component of almost all our consumer electronics.
    View the full article HERE

  • Why You Should Care About Narrowband IoT: It's Not Just a Fashion Trend (Cadence IP Blog - Meera Collier, Cadence)
    I read Paula Jones’ recent blog post about NB-IoT applications, and it led me down the rabbit hole: what is narrowband IoT, and why are companies using the Cadence Fusion DSP IP in applications that use it? IoT is the internet of things, which includes everything from mobile phones to smart refrigerators to sensors on cars to industrial equipment to anything, really, that is connected to the internet. The number of IoT-connected devices in 2018 now numbers more than 23 billion devices and is predicted to grow at a steady pace with no lag in sight. These sensors/devices are connected to the cloud through a variety of methods: cellular, satellite, Wi-Fi, Bluetooth, low-power wide-area networks (LPWAN), or connecting directly to the internet via ethernet.
    View the full article HERE

  • How DFI 5.0 Ensures Higher Performance in DDR5/LPDDR5 Systems? (VIP Experts Blog - Synopsys)
    The growth of datacenter, storage, automotive and other emerging market applications is driving the development of next-generation memory technologies – DDR5, LPDDR5. Like their predecessors, the latest memory technologies also use DFI, a standard interface between memory controller and PHY, to reduce the integration cost and increase performance and data throughput efficiency. DFI also has evolved along with the memory technologies, and next generation DFI 5.0 is here to ensure higher performance in the systems using DDR5/LPDDR5. In this blog, we will discuss the new features of DFI 5.0 specification. DFI defines signals, timing, and functionality required for efficient communication across the interface. The specification is developed for design of both memory controller and PHY, but does not place any restrictions on how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices.
    View the full article HERE

  • RISC-V is about to open the door to a wave of new chip startups in India (UltraSoC Blog - Gajinder Panesar, UltraSoC )
    CTO Gajinder Panesar looks ahead to the RISC-V Workshop in Chennai and the opportunity for India. Last year, we suggested that there’s a growing appetite in China for RISC-V, a suggestion that has turned out to have been spot on. Next week, on the 18th and 19th July, a RISC-V Workshop will be held at the India Institute of Technology Madras, in Chennai. I’ll be presenting on the topic of: ‘It’s not about the core: It’s about the system‘. Why India, and what’s so exciting about the opportunity?
    View the full article HERE

  • A Decade of Building CODECs with High-Level Synthesis (Cadence IP Blog - Sean Dart, Cadence)
    Over the past decade, we have seen a dramatic increase in the size of common video formats. Addressing this has required an evolution in the performance and complexity of video codecs, all the way from MPEG-2 to H.265. When designing hardware for these CODECs, high-level synthesis (HLS) has been a very common implementation tool of choice, due to the huge productivity gains provided by HLS and the ability of designers to easily experiment with multiple architectural choices (“design space exploration”). The HLS team here at Cadence® has watched customers build these designs all over the world, and we have the passport stamps to prove it. We have seen multiple approaches to implementing various CODECs, and I wanted to describe some of the experiences we have seen and hopefully provide some useful advice should you be looking to start such a design.
    View the full article HERE

  • Microchip release first Arm Cortex-M23 based chip bringing new levels of security for constrained IoT devices (arm Blogs - Kobus Marneweck, Arm)
    Imagine a future of one trillion connected devices around the globe – in our cars, homes, hospitals, workplaces, streets. Well, everywhere. How do we ensure that even the most tiny, low-power devices authenticate users, ensure personal information is encrypted and maintain enough battery life to do all of that efficiently and securely? It is only with semiconductor, systems and software companies adopting more secure technology will we see more secure devices entering the market. Microchip announced the first chip families available based on the Arm Cortex-M23 processor – the SAM L11 and the SAM L10 – with the SAM L11 based on TrustZone for Armv8-M, bringing a new level of trust and security to embedded systems. Since this chip is based on the familiar Cortex-M programming model, security is now even more accessible for embedded software developers. This technology enables product manufacturers to ensure a trusted foundation at the core of their most constrained devices, bringing robust protection for the valuable data being collected by even the smallest IoT devices.
    View the full article HERE