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Design And Reuse - Headline News
The industry source for engineers and technical managers worldwide.

Design And Reuse - Industry Expert Blogs
  • Despite losses Arm stands by commitment to double UK headcount (Mannerisms - David Manners)
    Arm CEO Simon Segars says the company will meet the commitment to double its UK headcount made when Softbank bought Arm in July 2016. The commitment still stands despite Arm becoming loss-making. In Q3 Arm made an operating loss of $11.3 million while Softbank made a loss of $6.4 billion.
    View the full article HERE

  • Functional Safety: It's not just about cars (With Imagination Blog - Jo Jones, Imagination)
    Functional safety, or FuSa, is a term that we’re increasingly discussing with our customers and prospects, particularly in association with automotive and autonomous vehicles. Imagination is now on a journey that will ensure that it can offer its customers FuSa certifiable or FuSa certified IP in the automotive space. However, while automotive gets much of the attention it’s important to acknowledge that FuSa doesn’t just apply to the automotive industry. Other industries, such as aviation, marine, industrial and healthcare, are also benefiting from system, device, machine and equipment safety. Functional safety provides assurance for safety-related functions within the product itself. Safety mechanisms built into the product can reduce the probability that a hazard will occur by detecting a fault and, if possible, maintain or return the system to a safe state. A good example would be the detection of smoke by a fire alarm and the activation of sprinklers or other firefighting initiatives to stop the fire spreading.
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  • Is Design in India on the Upswing? (The India Circuit Blogs - Madhavi Rao, Cadence)
    The India Electronics and Semiconductor Association (IESA) recently organized a two-day conference on Strategic Electronics, and, not surprisingly, the overriding message was that India needs indigenous chip design and wafer fabrication facilities for its development of Defense and Space electronics. While the debate on whether or not India needs a wafer fab continues on and off, there is no denying that indigenous chip design is on the upswing – and not just in the Defense sector. This is not to be confused with the cutting-edge work happening at captive design centers of multi-national corporations; we are talking about Indian companies designing and launching chips that are 100% designed in India.
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  • Softbank reports $6.4bn Q3 loss (Mannerisms - David Manners)
    Earlier today, Arm’s owner SoftBank reported a $6.4 billion loss for Q3 as a result of re-valuations of its investments in its Vision Fund. The value of 25 Vision Fund companies was marked down. “There was a problem with my own judgment, that’s something I have to reflect on,” said Softbank CEO Masayoshi Son (pictured).
    View the full article HERE

  • Managing NVME Verification Complexity (VIP Experts Blog - Synopsys)
    From inception, NVMe was designed to support multiple hosts accessing shared media. Early implementation included PCIe in-the-box devices such as Endpoint(EP), Root complex(RC) and Root complex integrated endpoint(RCiEP); over time, Cloud and Storage infrastructure created a need for remote storage. NVMe implementation can address space occupied by both SATA point-to-point architecture and SAS. Successful adoption in both spaces is due to the promise of low latency and a common interface for storage, regardless of location. Though the verification challenges in these two use cases are similar, they still require a different thought process.
    View the full article HERE

  • Industry's First Verification IP for Arm AMBA5 CHI-D Enables Early Adopter Success (VIP Experts Blog - Synopsys)
    Synopsys offers a broad set of verification solutions for next generation Arm® AMBA® protocols, including AMBA5 CHI Issue D(CHI-D), and verification automation solutions including VC AutoTestbench for Testbench Generation and VC Autoperformance for Performance Verification of ARM based protocols, which designers have widely adopted and achieved numerous tape-out successes. We continue the rapid expansion of Synopsys’ verification solutions for AMBA protocols and strengthen our leadership with our latest offering of VIP for AMBA ACE5 and AXI5, which are already in use by early adopters of the new specifications. Synopsys VIP for the AMBA5 CHI Issue D (CHI-D) specification enabled early customers and partners to extend the standard architecture for their next-generation coherent designs with new enhancements for increased performance. Let’s dive down to understand more about the new features and latency optimization techniques available in AMBA5 CHI Issue D. Coherency is the crux to most of the today’s complex SoCs targeting wide range of applications, such as: mobile, networking, AI/machine learning, automotive, and data centers. CHI is built on the same coherency protocol that is used in AMBA 4 ACE. CHI operates on the concept of Nodes and Interfaces, rather than the Master/Slave paradigm used by previous AMBA protocols. A CHI master is termed as Request Node (RN), CHI slave is termed as Slave Node (SN). The CHI interconnect consists of one or more Home Nodes (HN).
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  • US pressures TSMC not to fab Huawei ICs (Mannerisms - David Manners)
    Washington is leaning on Taipei to instruct TSMC to stop fabbing Huawei’s ICs, reports the FT. Sales to China represent about 20% of TSMC’s total sales and it is thought that about half of that 20% is accounted for by sales to Huawei.
    View the full article HERE

  • Why your DL accelerator should be replaced (videantis Blog - Marco Jacobs)
    Intelligence is quickly being added to all our electronics devices. Whether it’s our vehicles that automatically brake when things get dangerous, our phone’s cameras that ensure every picture we take looks great, or our datacenters that need to not just store and distribute our videos, but also understand what’s in them – intelligent image processing using deep learning is everywhere. But just adding a deep learning accelerator next to a chip’s host CPU subsystem doesn’t mean you have a chip that can handle all the required visual computing tasks. While we’ve seen some designs that didn’t realize this, many SOCs these days do have multiple compute engines for the different imaging-related processing duties.
    View the full article HERE

  • Implementing Automotive Radar on Tensilica Processors (Breakfast Bytes - Paul McLellan)
    The big controversy about sensors in autonomous driving is whether lidar is essential. Radar has improved significantly in resolution and so I like to phrase the question as to whether radar is getting better faster than lidar is getting cheaper. Today's focus is on radar since the technology is playing an increasingly important role, driven by automotive ADAS applications. These applications require higher performance and more capabilities from the radar module to determine distance, direction, and speed of targets in a multi-target scenario. The radar technology used is known as frequency modulated continuous wave (FMCW), typically in the 77GHz band. Instead of putting out individual radar pulses and measuring the time-of-flight for the echo to return, the radar is transmitted continuously but with frequency varying, typically in a linear sawtooth wave.
    View the full article HERE

  • Incredibly Scalable High-Performance RISC-V Core IP (Sifive Blog - )
    Introducing the new SiFive U8-Series Core IP SiFive is pleased to introduce the SiFive U8-Series Core IP, an incredibly scalable high-performance microarchitecture for modern SoC designs. The SiFive U8-Series is the highest performance RISC-V ISA based Core IP available today, based on a superscalar out-of-order pipeline with configurable pipeline depth and issue queue width. SiFive U8-Series Core IP is designed for use in performance- and latency-sensitive markets, such as automotive, datacenter attach, and edge or end point deep learning SoCs. The needs of the modern world to solve problems using deep learning and real-time low latency processing are increasing compute workloads in the enterprise, and migrating tasks into the edge and end point. Domain specific SoCs are being used to localize compute to reduce latency, improve workload performance, and increase efficiency. The requirements of modern SoCs include scalable processor cores that span current process technology, enabling configurable designs, and permit customization.
    View the full article HERE

  • PCIe 5.0 Equalization Modes: Reducing Link Bring-Up Time (VIP Experts Blog - Synopsys)
    Billions of internet-connected devices and data-intensive real-time applications are expected to appear on the market in the near future and 100 Gigabit Ethernet (GE) speeds, common in data centers today, will just not be fast enough to handle the bandwidth. Therefore, we’re already anticipating the need for data center operators to migrate their networks from 100 GE to 400 GE, creating demand for faster memory and faster serial bus communications. PCIe is a high-speed, differential, serial standard for point-to-point communications. Each new generation of the PCIe standard offers additional features and faster data transfer rates than the previous generation. The latest generation, PCIe 5.0, will double the throughput rate of PCIe 4.0. The transfer rate of PCIe 5.0 is 32 gigatransfers per second (GT/s) versus the 16 GT/s supported by PCIe 4.0. With 64 gigabytes per second (GB/s) of unidirectional transfer bandwidth, PCIe 5.0 provides data throughout at 128 GB/s of bidirectional traffic.
    View the full article HERE

  • Arm TechCon 2019 - Recap (VIP Experts Blog - Synopsys)
    Arm TechCon was successfully held at San Jose Convention Center on 8-10th October, 2019. Synopsys protocol experts were there demonstrating our verification solutions for attendees from a wide spectrum of markets like IoT, mobile, automotive, and consumer. On Wednesday, Satya Acharya, Sr. Applications Engineer Manager, presented a session on Synopsys’ verification automation solution to generate a scalable and reusable design verification environment to perform functional and performance verification using the Arm Adaptive Traffic Profile for AI/ML-based systems. AI designs typically require exploring multiple architectures, which in turn require a fast and scalable design verification environment that can be used to manage multiple levels of verification. Current verification environments don’t scale well from the block to SoC level. They lack infrastructure for performance-based verification and are effort-intensive and time consuming to build, along with being inherently error-prone because of the required manual intervention. Therefore, there is a pressing need for automation in the overall SoC verification process. Synopsys verification automation solution combined with Verdi debug comes to your rescue.
    View the full article HERE

  • Arm helps Softbank to a tax-free year (Mannerisms - David Manners)
    Arm helped its owner Softbank reduce its tax bill to zero in a stratagem which Japan’s taxman is looking to shut down for the future, reports the Nikkei. The tax trick is to transfer a subsidiary’s core business to the parent, sell off the company for a cheap price to a subsidiary and then set the difference between the purchase and sale prices as a loss against taxes. In March 2018, a three-quarters stake in Arm’s core business – Arm Ltd – was transferred to the Softbank parent company. This depressed Arm Holdings’ value.
    View the full article HERE

  • AMBA moves forward with major revisions to AXI and CHI specifications (arm Blogs - Francisco Socal, Arm)
    We are pleased to announce two major revisions of the AMBA specifications: Issue G of the AMBA AXI and ACE Protocol Specification and Issue D of the AMBA CHI (Coherent Hub Interface) Architecture Specification. These releases are part of the existing fifth generation of AMBA (AMBA 5) and extend the successful and widely adopted AXI and CHI interfaces. They introduce the support for key Arm Architecture features and a series of performance and transaction improvements that are aligned with the requirements for the next generation of system on chips (SoCs). This blog post gives an overview of some of the functionality introduced in the new releases of the AXI and CHI specifications.
    View the full article HERE

  • PCIe 3.0 Still Shines While PCIe Keeps Evolving (Cadence IP Blog - William Chen, Cadence)
    PCIe has been widely adopted in the electronics industry since its first debut in 2003 (PCIe 1.0 standard release) for wide breach of applications, from Data Center Server, Networking, to Mobile, AI/ML, Automotive, IoT, and many others…. It’s a versatile, high-performance, robust, mature interconnect standard with full “backward compatibility” (e.g., a PCIe 3.0 device can still function well in a PCIe 4.0 system) which enables a solid and strong PCIe eco-system in the industry. While the market, so as the users, are enjoying the systems, e.g., desktop/laptop, powered (or to be more specific: “bridged”) by PCIe 3.0 since 2010, the industry is pushing hard for the PCIe 4.0 eco-system enablement. Earlier this year, AMD announced it X570 chipset would support the PCIe 4.0 interface and Phison also introduced the world’s first PCIe 4.0 SSD. On the standard evolution front, the official PCIe 5.0 came out in May 2019, doubling the data rate to 32GT/s from 16GT/s in PCIe 4.0. The PCIe 6.0 standard will be released in 2021 based on the announcement made by PCI-SIG in June’19 with the goal to further double the data rate to 64GT/s with incorporating the PAM4 coding.
    View the full article HERE

  • You Can Still Register for Silvaco SURGE Users' Event in SV, Oct 24 (Silvaco Blog - Graham Bell, Silvaco)
    SURGE brings the TCAD, EDA, and IP communities together to discuss new technologies, explore smart application integration, and discover innovative techniques for advanced semiconductor design. The event includes eight demo stations, a catered lunch, and cool prizes and giveaways for attendees. Executive keynotes Technology Tracks: TCAD, EDA and Design IP Roadmap presentations Customer and partner presentations and success stories Eight unique demo stations Networking with industry experts Silicon Valley, USA Thursday October 24, 2019 Santa Clara Marriott, 2700 Mission College Boulevard, Santa Clara, CA 95054 Click Here to Register
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  • Arm TechCon: The Keynotes (Breakfast Bytes - Paul McLellan)
    Simon Segars opened Arm TechCon with a new look, having discovered that real men have beards. This is the 15th Arm TechCon. In this post I'm going to focus on the new things that Arm announced during the keynotes. Simon Segars Back when TechCon started, Simon reminisced, digital cell phones had finished their period of explosive growth and nobody knew what was coming next. Then smartphone came along and had their period of explosive growth. Now growth has slowed again. But there are still enormous opportunities ahead in mobile in what will turn out to be a new era of computing, The 5th Wave of Computing. Intelligent semiconductors are becoming ubiquitous. There are 150B chips shipped based on Arm products. It took roughly 50 years for the first 50B Arm chips, the next 50B took just two years. That first 50B will seem like a warm-up act as we move towards a trillion connected devices.
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  • The Economist on RISC-V and Indian Semiconductors (Breakfast Bytes - Paul McLellan)
    Our industry is difficult to understand. Most of us resort to imperfect analogies to explain it when we have to. Some of this is because we have a complex supply chain for creation. It is easy to get confused between an instruction set architecture (ISA, like x86), microprocessor IP (like Arm processors), an SoC containing a microprocessor (any smartphone application processor), a chip that is an entire microprocessor (many Intel products), a fabless semiconductor company (say NVIDIA), a foundry (GlobalFoundries), a fab (like Fab 1 in Dresden), subcontract manufacturing (like Foxconn in Shenzhen). And confusingly, some companies do multiple things: for example, Samsung is a foundry, has fabs, is in the memory business, sells smartphones, TVs, solid-state disks (SDD), and more.
    View the full article HERE

  • Sensor Fusion and ADAS in TSMC Automotive Processes (Breakfast Bytes - Paul McLellan)
    At the recent TSMC OIP Symposium, Cadence's Tom Wong presented Sensor Fusion and ADAS SoC Designs in TSMC 16FFC and N7. These two processes are the "compact" 16nm process and the mainline 7nm process, two processes that TSMC selected for adding additional characterization and manufacturing tracking to support the automotive end-markets. There are four big drivers in automotive electronics: 5G and DSRC (for V2x, and cloud communication) The growth of increasingly autonomous driving (broad level 2+ deployment) Vehicle electrification (2M in China, 1M in US, $100/kWh of battery) Smart mobility and ride-sharing (long term reliability) In this post, I am going to use the term EV for electric vehicles. In China, these are called NEV, for new energy vehicle. Hybrids, whether chargeable or not, are also in there with similar requirements (along with the need for an internal combustion engine, which is not today's topic). I'm also going to assume you know your autonomous driving levels, and the tiered nature of the traditional automotive supply chain.
    View the full article HERE

  • HBM Performance Verification Made Easy (VIP Experts Blog - Synopsys)
    HBM2E (High Bandwidth Memory) is a high-performance 3D-stacked DRAM used in high-performance computing and graphic accelerators. It uses less power but posts higher bandwidth than graphics cards relying on DDR4 or GDDR5 memory. Validating the performance and utilization of memory is a big challenge for users due to complex structure of SoC and the subsystem attached to it such as memory subsystem, interconnect bus, and processor. Synopsys’ Verdi Performance Analyzer provides a solution. This blog will provide insight into how Verdi Performance Analyzer natively integrated with Synopsys VIP can be used to measure key performance metrics like number of commands, count of page empty scenarios that occur in a test. All of these metrics can be used for performance benchmarking.
    View the full article HERE