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Design And Reuse - Industry Expert Blogs
  • What Happens in a Patent Lawsuit? (Breakfast Bytes - Paul McLellan)
    One of the presentations in the exhibit hall, at the Chiphead Theater, was What Happens in a Patent Lawsuit? which was presented by John Strawn and Tom Millikan. I have written about patents a couple of times on Breakfast Bytes, in Patents and Standards, Managing the Challenge and in Lawyers, Guns, and Money: An Evening with EDAC on Patents. This presentation was not about the process for getting a patent granted, or whether patents for business processes like Amazon's one-click should be granted. It was purely about the process of a patent lawsuit, and what to expect if you get involved in one. The first presenter was John Strawn, who has been an expert witness many times. The second was Tom Millikan, who is a lawyer. But he is not the usual lawyer, who got a bachelor's degree and immediately went to law school. He worked at Texas Instruments as a chip designer for years, before deciding that being a lawyer was more interesting than designing chips (hard to imagine). So he is obviously pretty technical too.
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  • Arm is changing machine learning experiences: Project Trillium (arm Blogs - Jem Davies, Arm)
    Imagine you’re 30 meters down, diving above a reef surrounded by amazing-looking creatures and wondering what species the little yellow fish with the silver stripes is. You could fumble around for a fish chart, if you have one, but what you really want is an easier and faster solution. Fast forward to 2019, and technology has provided. Now your waterproof smartphone is enabled by Arm Machine Learning (ML) and Object Detection processors. Your experience is very different. Your dive mask is relaying information in real-time via a vivid heads-up display. An Arm-based chip inside your smartphone is now equipped with an advanced Object Detection processor that is filtering out the most important scene data while an operating system tasks a powerful Machine Learning processor with detailed identification of fish, other areas of interest and hazards. The information you’re receiving is intelligently filtered, so you’re not overwhelmed with data. This is exactly what Arm’s Project Trillium and our new ML technologies will enable and much, much more.
    View the full article HERE

  • Secure Development Lifecycle for Hardware Becomes an Imperative (EETimes Blog - Jason Oberg, CEO, Tortuga Logic Inc. )
    Given recent events, its time for chip makers to take a page from the software vendor handbook and step up their game in heading off potentially costly threats. A Secure Development Lifecycle (SDL) for hardware with appropriate hardware security products could have prevented the recent Meltdown and Spectre vulnerabilities affecting Intel, ARM and AMD processor architectures. An SDL is the process of specifying a security threat model and then designing, developing and verifying against that threat model. Many in the software domain are familiar with SDL, which is a process invented by Microsoft to improve the security of software. To make this process as efficient as possible, the software domain is filled with widely deployed static and dynamic analysis tools to provide automation around security review for various stages of the development lifecycle.
    View the full article HERE

  • Machine Learning And Design Into 2018 - A Quick Recap (SemiWiki - Alex Tan)
    How could we differentiate between deep learning and machine learning as there are many ways of describing them? A simple definition of these software terms can be found here. Let's look into Artificial Intelligence (AI), which was coined back in 1956. The term AI can be defined as human intelligence exhibited by machines. While machine learning is an approach to achieve AI and deep learning is a technique for implementing subset of machine learning. During last year 30-Year Anniversary of TSMC Forum, nVidia CEO Jen-Hsen Huang mentioned two concurrent dynamics disrupting the computer industry today, i.e.,how software development is done by means of deep learning and how computing is done through the more adoption of GPU as replacement to single-threaded/multi-core CPU, which is no longer scale and satisfy the current increased computing needs. The following charts illustrate his message.
    View the full article HERE

  • Synopsys supports launch of Arm AMBA 5 AXI5, ACE5 protocols with 1st source code test suite and VIP (arm Blogs - Phil Dworsky, Synopsys)
    Through a blog post by Jeff Defilippi, Arm has just announced the new Arm AMBA 5 AXI5, ACE5 and ACE5-Lite protocols; you can request the the latest AMBA 5 specs through a link in that blog. These protocols are employed by Arm's latest technology, including DynamIQ processors like Cortex-A55 and Cortex-A75 as well as the Arm CoreLink CMN-600 Coherent Mesh Network. In his blog, Jeff does a great job of introducing the new features and benefits of these protocols, including the many updates and enhancements to AXI, ACE and ACE-Lite. Synopsys is proud to have collaborated with Arm on the development of this new AMBA 5 AXI5 and ACE5 specification and also deliver the first source code test suite and Verification IP (VIP) for these new protocols. In his blog on this new offering, Ankur Jain talks about the early adopter customer success using these products, which were developed concurrently with the specification.
    View the full article HERE

  • PCIExpress is everywhere ! and a USB joke from a PCIe expert (To USB or Not to USB: A USB IP Blog - Eric Huang, Synopsys)
    Why did the USB guy fail the multiple choice test? Answer at the bottom of the blog PCIExpress is Everywhere! I asked Richard Solomon, our USB Technical Marketing Manager, “Why is PCIExpress everywhere?”: “Everywhere there’s not a cable perhaps – USB to connect things across cables, PCIe for everything else. It IS kinda amazing that we’ve got small M.2 form-factors for PCIe/NVMe SSDs, tons of WiFi chips with PCIe, so lots of random gear with WiFi has PCIe in it. Likewise the SSD connections – they’re great for industrial stuff so Internet Of Things tend to have a lot of small PCIe connections in them for “stuff”. Not too many OCuLink cabled external disks, Blu-Ray drives, etc though. Don’t forget automotive – your little “lane assistant” is pretty much a 1980s supercomputer and it’s using PCIe to connect processor cores.”
    View the full article HERE

  • PowerVR virtualization and the Series8XT: geared for automotive (With Imagination Blog - Gautham Kripalani, Imagination Technologies)
    Over the last few years the concept of virtualization – separating software from the hardware on which it is run – has become familiar to many. In this post, we will describe what virtualization is, and look how it works in PowerVR GPUs, and explain how this provides great benefits to various markets, in particular to automotive. On desktops, virtualization enables a computer to run more than one operating systems concurrently, so that, for example, a developer can run a Linux ‘guest’ operating system on a Microsoft Windows host machine, whereas in the enterprise space, it’s often used to consolidate workloads in order to decrease CapEx and OpEx. In embedded platforms, the primary purpose is to lower costs while also ensuring security through separation.
    View the full article HERE

  • AI-Leader Horizon Robotics Selects NetSpeed AI-based NoC IP For Next Generation Designs (SemiWiki - Mitch Heins)
    If you haven’t noticed, there has been a BIG influx of money into Artificial Intelligence (AI) technologies. Most recently, the Chinese government announced that AI is one of their top initiatives with a goal to catch up with the United States within 3 years and to be the world leader in AI by the year 2030. Horizon Robotics, founded in 2015, is one of China’s AI startups. It just closed a $100M A-round funding led by Intel Capital in October 2017 with the intent to build AI-based hardware and software targeted for use in autonomous vehicles, smart homes and smart cities. They plan to differentiate themselves by building low power, low cost intelligent processors that will enable devices to perceive, interact, understand and make decisions locally in the fog instead of having to transmit data to the cloud.
    View the full article HERE

  • Bullish Chip Forecast Explained (EETimes Blog - Malcolm Penn)
    Future Horizons' CEO explains why the market watcher just increased a 2018 semiconductor forecast that was already the most bullish in the industry. A recently-published chart from the SEMI trade group (below) summarizes the 2018 semiconductor revenue forecasts from the various industry watchdogs. This clearly shows the global collective received wisdom for 2018 chip revenues in the 7-8 percent range. Cowan’s linear regression model is the most bearish at 5.9 percent, and Future Horizons is out on a limb at a bullish 16.0 percent. The overall forecast average was 8.3 percent, or 7.2 percent if you exclude our somewhat contrarian position, signalling the end of 2017’s boom. While other forecasters were blotting the ink on their single-digit growth numbers, we were revising our 2018 forecast up to 21 percent, significantly higher than the 16 percent we posted in September 2017. That now placed us almost three times higher than the overall industry view. Readers familiar with Future Horizon’s research methodology will know that we base our industry analyses on the behavior of what we call the four horsemen of the semiconductor apocalypse--the global economy, IC unit demand, wafer capacity and semiconductor ASPs. These factors combine, albeit in a mathematically indeterminant way, to drive semiconductor revenue market growth. A strong economy stimulates demand for IC units, wafer fab capacity determines the supply and demand balance/imbalance which in turn sets the foundation for ASPs.
    View the full article HERE

  • Microprocessor Systems Require End-to-end Security (EETimes Blog - Erez Kreiner, Co-founder, NanoLock Security)
    Much has been written, said and tweeted about the Meltdown and Spectre security flaws in the month since they were unveiled, but the reality is that this conversation is just getting started. The staggering number of microprocessors that are impacted by these critical, design-level security vulnerabilities in modern CPUs (billions of existing devices) pales in comparison to the number of smart, connected and deeply vulnerable devices that will exist in just a few more years. All of these “endpoints,” including pervasive edge devices like phones, cars, industrial control systems, smart meters and consumer goods, will be susceptible to malicious hacking unless the processor industry starts to think creatively and act swiftly to protect the entire chain of vulnerability. Intel, ARM, Qualcomm, AMD and others have leapt into action, working to develop an industry-wide approach to resolve this issue promptly and constructively. And to be fair, these newly-revealed vulnerabilities represent architecture-level design flaws that date back more than 20 years, when few people could have imagined such a wholly connected world of vehicles, homes, buildings, and automated factories and utilities — all reliant on a massive profusion of microprocessors. Even when we look at the short term, the ability of designers to predict how devices will look and behave three to five years from now is questionable, not to mention untrustworthy.
    View the full article HERE

  • What's the Deal with ISO 26262? (Cadence on the Beat Blogs - Meera Collier, Cadence)
    Last time I had a flat tire, I pulled my truck into one of those side-of-the-road gas stations. The attendant walks out, looks at my truck, looks at me, and I swear he said, Tire go flat? I couldn’t resist. Said, Nope. I was driving around and those other three just swelled right up on me. — Bill Engvall We recently took a road trip to Las Vegas in which we drove from Santa Cruz, about a 7-hour drive. On the day that we started the trip, we drove all of about six miles before a warning light came on: Left rear tire pressure alert! With an exclamation point! So it must be urgent! But there was no telltale floompah floompah sound of a flat tire. I pulled over and inspected the tire. It seemed perfectly fine. It didn’t seem at all flat. Later in the trip, with the alert signal still illuminated, we even checked the tire pressure using the appropriate tools. It was fully up to specifications. So what was going on?
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  • Build and run Linaro deliverables with Arm Fast Models (arm Blogs - Jason Andrews, arm)
    Linaro provides a complete software stack for secure boot, u-boot, and Linux. This article explains how to build and run this software on Arm Fast Models. Although there is some existing information on this topic, there are two assumptions that often create challenges when trying to apply the Linaro deliverables to an actual project. These are: Host operating system differences Target hardware configuration changes This article provides some confidence that the Linaro deliverables can be adapted when a project is a little different from the default assumptions. It also provides some insight into what is really happening and how to debug the flow when just following the instructions doesn’t work.
    View the full article HERE

  • New AMBA 5 ACE/AXI Specification: Rationale for Atomic Transactions (Cadence IP Blog - Dimitry Pavlovsky, Cadence)
    The recent update of the AMBA® 5 ACE/AXI specification introduces a number of significant performance improvements which help to align the protocol to the more recent AMBA® 5 CHI (Coherent Hub Interface) specification. One of the most prominent features is introduction of atomic transactions. Before we take a close look at this new class of transactions, let’s look back in time. Previous generations of AMBA ACE/AXI protocols have included support of exclusive accesses which relied on the semaphore-type operations. A typical exclusive access had the following steps:
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  • Taking a closer look at the Rambus GDDR6 PHY IP Core (Rambus Blog - )
    Once targeted exclusively at GPUs, GDDR use cases are rapidly expanding beyond traditional GPU and graphic applications. This is primarily due to the demand for increased bandwidth across a diverse set of market verticals – including the data center and automotive sector. GGDR6 can help meet that demand. Bandwidth and SI challenges More specifically, DDR4 currently tops out at 3.2 Gb/s, while a maximum interface speed of 8 Gb/s is achievable with GDDR5. In contrast, GDDR6 devices will double interface speed to 16 Gb/s. Put simply, GDDR6 is expected to provide 5x the speed per pin of leading-edge DDR4, with the Rambus GDDR6 PHY supporting speeds up to 16Gbps per pin, across two 16bit channels to provide a maximum bandwidth of 512 Gbps (or 64GB/s). With GDDR6 providing a maximum bandwidth of up to 64 GB/s, it is critical for ASIC designers to ensure that devices and systems aren’t affected by signal integrity issues. This is precisely why the Rambus GDDR6 PHY engineering team makes extensive use of modeling and simulation tools, as well as providing highly programmable circuits, debug interfaces and utilities. Moreover, our engineering team comprises a range of in-house experts that participate in all stages of the GDDR6 PHY design which will be available on leading FinFET process nodes. These include package and PCB design experts and layout gurus, as well as signal integrity and power integrity specialists.
    View the full article HERE

  • Open-Source IP in Government Electronics (Breakfast Bytes - Paul McLellan)
    At the RISC-V conference late last year, one of the keynotes was by Linton Salmon titled A Perspective on the Role of Open-Source IP in Government Electronic Systems. It was not specifically about RISC-V, although the RISC-V ISA and many of the implementations to date (but not all) are open source. Linton started giving a little of his background. He is a Program Manager at DARPA/MTO. These program managers are people pulled from academia or industry to work for the government for a few years. His background is in both. He was a professor in EE and physics at BYU and Case-Western and then had 15 years in different executive positions directing R&D at GF, TI, and AMD. He was even a member of the steering committee on the first ITRS. He calls himself "middle-aged" meaning that he has been in his government position for three years. The institutional memory is all in the contractors, the program managers are all "temporary".
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  • Imagination's view: The key trends at CES 2018 (With Imagination Blog - )
    As we do every year, earlier at the start of January Imagination attended the CES 2018 show in Las Vegas, and so we thought it was time we take a look back at some of the overall trends that we saw coming out of the show. With the rise of car-tech and autonomous driving, many believe that CES is now an automotive show before anything else. It makes sense then to start with the thoughts of Bryce Johnstone, the Director of Ecosystems, Segment Marketing, Automotive, at Imagination. At CES this year there were four key trends. – The Chinese are coming – Screen, screens, screens – Advanced dashboard interaction – Level 4 and Level 5 autonomous driving and software!
    View the full article HERE

  • Introducing the next generation of AXI and ACE protocols (arm Blogs - Jeff Defilippi, arm)
    Arm is happy to announce the release of the next generation of AMBA 5 ACE5 and AXI5 protocols. A number of capabilities have been added over the prior AMBA 4 generation to align with AMBA 5 CHI. The protocols have been implemented in Arm’s latest technology including DynamIQ processers such as Cortex-A75 and Cortex-A55 along with the CoreLink CMN-600 Coherent Mesh Network. To recap, here are the 3 main protocols included within the ACE and AXI specification: AXI (Advance Extensible Interface) – AXI provides connectivity for non-coherent masters and slaves ACE (AXI Coherency Extensions) – Supports full coherency for masters with caches such as Cortex-A processors. ACE-Lite – Supports IO coherency for masters without caches (Accelerators, IO, etc) that share coherent memory space.
    View the full article HERE

  • Industry's First Source Code Test Suite and Verification IP for Arm AMBA ACE5 and AXI5 Enables Early Adopter Success (VIP Experts Blog - Synopsys)
    Synopsys offers a broad set of verification solutions for next generation Arm® AMBA® protocols, including AMBA CHI Issue B, and verification automation solutions including Auto SoC Testbench Generation and AutoPerformance for AMBA protocols, which designers have widely adopted and achieved numerous tape-out successes. We continue the rapid expansion of Synopsys’ verification solutions for AMBA protocols and strengthen our leadership with our latest offering of source code test suites and VIP for AMBA ACE5 and AXI5, which are already in use by early adopters of the new specifications. Arm just announced the availability of AMBA ACE5 and AXI5 as a part of the AMBA 5 family of protocols, enhancing the standard architecture for next-generation interconnect designs. Synopsys has collaborated with Arm on the creation of this specification and to deliver Synopsys VIP for ACE5 and AXI5 with increased performance for faster verification closure. Synopsys’ VIP for ACE5 and AXI5 is industry’s first source code test suite and VIP for the latest AMBA specifications.
    View the full article HERE

  • JEDEC UFS 3.0 Now Available in Cadence VIP Portfolio - For Mobile and Automotive Markets (Cadence IP Blog - Thierry Berdah, Cadence)
    The JEDEC UFS (Universal Flash Storage) started in 2011 with the v1.0 first specification version, supporting a bandwidth of 300 MB/s per lane. Since then JEDEC has been continuously releasing new UFS specification versions on top of the MIPI UniPro® and MIPI MPHY® evolving specs. UFS is now evolving to a new version of 3.0, reaching a total bandwidth of 2.4 GB/s. It seems that UFS keeps on slowly winning over eMMC in the mobile market, replacing it in the high end mobile and slowly taking over in the medium/low end as well. But UFS is not stopping there, after taking over the mobile market it is now entering the automotive market and ready to conquer its next target. New cars are requiring more sophisticated systems with automotive information and entertainment systems and ADAS with more storage requirements for automotive applications. UFS supports their high performance and density needs providing a suitable solution.
    View the full article HERE

  • Arm support for Android NNAPI gives >4x performance boost (arm Blogs - Robert Elliott, arm)
    The launch of Arm support for the Android Neural Networks API (NNAPI) sees the release of open-source, optimized neural network operators that deliver significant performance uplift across CPUs and GPUs Back in May at Google I/O, we heard the first public news about TensorFlow Lite for Android. This was the first exciting hint of a major new API that will affect the deployment of neural networks on Arm-based platforms supporting Android. Inference engines are nothing new, but the big change with the announcement of NNAPI is standardized support within Android and the ability to target the wide array of accelerators available from the Arm ecosystem, such as the Arm Mali GPU. At Arm, we fully support this development and will be releasing support for our Arm Cortex-A CPUs and Mali GPUs from day one. This is following on from other efforts to improve the performance of machine learning applications on Arm platforms, adding to our existing release of the Compute Library at the beginning of the year, and our ongoing engagement with the community of companies and developers that is standardizing approaches and sharing developments in the open.
    View the full article HERE